The present invention relates to a semiconductor memory device, and more particularly, to a power-up circuit for generating a stable power-up signal.
Generally, devices which perform analog circuit operations are designed to have a reference voltage and may operate at a specific voltage. If a device operates at an undesired voltage level that may be caused when a reference voltage significantly changes during operations or fails to be reset, characteristics of the device deteriorate and productivity of the device is decreased.
Varying characteristics during the operation of devices can be can be compensated/offset/reduced by adding a capacitor, a regulator circuit or a calibration circuit. Using an appropriate initial value before the supply of power is mostly determined by a power-up circuit. If the power-up circuit fails to apply an accurate initial level, a target level may not be provided during operation or within a certain time required in a specification. Therefore, a semiconductor memory device does not operate in response to a voltage level of an external power supply voltage immediately after the external power supply voltage is applied, but operates after the power supply voltage rises higher than a certain level. For this reason, a semiconductor memory device typically includes a power-up circuit.
The power-up circuit protects an overall semiconductor memory device from being damaged by a latch-up or the like when an internal circuit operates before a voltage level of an external power supply voltage is stabilized. Hence, the reliability of an overall chip is improved. Therefore, the power-up circuit is designed to generate a power-up signal that rises with the voltage level of the external power supply voltage and becomes a low level (or a high level) when the external power supply voltage reaches a sufficient level.
FIG. 1 is a circuit diagram of a conventional power-up circuit.
When a device is turned on and a voltage level of a power supply voltage rises, a power-up circuit of FIG. 1 turns on a bandgap circuit which is a reference voltage generator.
As illustrated in FIG. 1, the power-up circuit includes two resistors R1 and R2 connected in series between a power supply voltage terminal VDD and a ground voltage terminal VSS. A PMOS transistor P1 and an NMOR transistor N1 are connected in series between the power supply voltage terminal VDD and the ground voltage terminal VSS. The PMOS transistor P1 is always in a turned-on state since its gate is grounded. A divided voltage generated by the resistors R1 and R2 is applied to a gate of the NMOS transistor N1. A power-up signal POWER_UP generated by the turn-on/turn-off operation of the PMOS transistor P1 and the NMOS transistor N1 is provided to a reference voltage generator (not shown) through an inverter INV1.
In the conventional power-up circuit having the above-described structure, the PMOS transistor P1 maintains a turned-on state because it receives a ground voltage as a gate voltage when a power supply voltage begins to be supplied (a state where a voltage level of the power supply voltage does not reach a voltage level enough to generate the power-up signal) Due to this operation, a voltage applied to an output terminal becomes a high level state and is inverted by an inverter INV1 to output a low signal. At this point, the power-up signal maintains the ground voltage.
Thereafter, the voltage level of the power supply voltage rises sufficiently, and the NMOS transistor N1 is turned on by a divided voltage generated by the resistors R1 and R2. In this case, the voltage applied to the output terminal becomes a low level state. The voltage is inverted by the inverter INV1 to output a high signal as a high level power-up signal. That is, the power-up signal level maintains the ground voltage and follows the voltage level of the power supply voltage from the moment when the high signal is generated. An internal circuit of a semiconductor memory device changes from a reset mode to an operation mode when the power-up signal level changes from a low level to a high level. The operation waveform diagram of this case is illustrated in FIG. 2.
In the conventional power-up circuit, however, if the usage of the power supply voltage inside the device rapidly increases, the voltage level of the power supply voltage being the power-up supply voltage is rapidly lowered and thus the power-up signal may not be generated normally, even though the external power supply voltage is constantly supplied. That is, the power-up signal is reset by the lowered power supply voltage, and the chip is reset by the resetting of the power-up signal, thus causing malfunctions.
In addition, the voltage level of the external power supply voltage used as the operating voltage of the semiconductor memory device is gradually lowered, and a power-up reset skew window is almost fixed according to process condition. Hence, a power-up reset signal variation range relative to a voltage level of the external voltage (VDD) is relatively significantly larger. Consequently, despite that the voltage level of the external power supply voltage reaches the operating level of the semiconductor memory device, the power-up reset signal is not generated at a proper time. Consequently, the internal circuit of the semiconductor memory device is not reset.